1. Field
One or more embodiments described herein relate to a method for rasterizing a mask layout and a method for fabricating a photomask using a method for rasterizing a mask layout
2. Description of the Related Art
A photolithography process may be used to fabricate a semiconductor device. This process involves using a photomask to print an integrated circuit layout onto a wafer. One type of photomask includes a transparent region and an opaque region. The transparent region may be formed by etching a metal layer on the photomask for emitting light. The opaque region blocks light. Together, the transparent and opaque regions form mask patterns for emitting a specific pattern of light onto the wafer that corresponds to the integrated circuit layout.
As the integration of semiconductor devices increases, the distance between the mask patterns decreases and the width of the transparent region becomes narrower. This proximity may induce light interference and diffraction which distorts the layout printed on the wafer. Resolution enhancement technology (e.g., optical proximity correction) may be used in an attempt to reduce this distortion.
One type of optical proximity correction involves predicting the degree of distortion that may occur. Based on predicted results, the photomask may be changed to produce correct mask patterns, which, in turn, are used to a produce a corrected layout printed on the wafer. Optical proximity correction may be performed, for example, based on a lithography simulation that predicts a contour image to be formed on the wafer from a designed mask layout. Rasterization of the mask layout may be required to perform the lithography simulation.